Programme - 16th January 2023 (PDF)

CET Morning Session
Chair - Christos Bouganis
10:00 - 10:05 Opening Address of WRC
10:05 - 10:30 Mixing analog and digital reconfiguration to achieve low energy and high performance in CNNs
Luigi Carro - Instituto de Informática, UFRGS
10:30 - 11:00 Most Resource Efficient Matrix Vector Multiplication on FPGAs (for Deep Learning Applications)
Marc Reichenbach - Brandenburg University of Technology
11:00 - 11:30 Coffee break
Chair - João MP Cardoso
11:30 - 12:00 An efficient and flexible stochastic CGRA mapping approach
Satyajit Das - Indian Institute of Technology Palakkad
12:00 - 12:30 How to use a CGRA without even knowing about it - AMIDAR Processors and its Successor
Christian Hochberger - TU Darmstadt
12:30 - 13:00 Implementing AI Robotic Algorithms in FPGAs
Yannis Papaefstathiou - ECE School, Aristotle University of Thessaloniki
13:00 - 14:00 Lunch
Afternoon Session
Chair - Kevin Martin
14:00 - 14:30 Developing HPC open source libraries: The OPTIMA experience
Dionisis Pnevmatikatos - National Technical University of Athens
14:30 - 15:00 Speculative Loop Pipelining in High-Level Synthesis
Steven Derrien - IRISA/INRIA/Université de Rennes
15:00 - 15:30 Variable precision sparse-dense matrix processing in Tensorflow Lite with dynamic reconfiguration
Jose Nunez-Yanez - Linkoping University
15:30 - 16:00 Coffee Break
PhD Forum
Chair - João Bispo
16:00 - 16:10 Luis Sousa, INESC TEC/University of Porto
16:10 - 16:20 Marc Rothmann, Osnabruck University,
16:20 - 16:30 Leo Udeji - University of Massachusetts Lowell
16:30 - 17:00 Round-Table discussion
The need, price & potential of reconfigurability: Now and in the future
Chair - Juergen Becker
Participants:
Luigi Carro, UFGRS, Porto Alegre, Brazil
Steven Derrien, Univ. Rennes + IRISA/INRIA, France
Dirk Koch, Univ. Heidelberg, Germany
Das Satyajit, IIT Palakkad, India
Dirk Stroobandt, Univ. Gent, Belgium
17:00 Closing of the workshop