EUC-2015 and CSE-2015 Special Sessions

 

Ø       Special Sessions on FET-HPC and Exascale Recently EU-Funded Projects [Oct. 23, 14:00-15:20]

Ø       Special Sessions on EU-Funded Projects on Embedded Systems: Platforms, Health-care and Assisted Living [Oct. 23, 15:50-17:05]

 

Special Sessions on FET-HPC and Exascale Recently EU-Funded Projects

Project:        EXTRA

 

Title:             EXTRA: Exploiting eXascale Technology with Reconfigurable Architectures

 

Authors:       Catalin Bogdan Ciobanu, Ana Lucia Varbanescu, Dionisios Pnevmatikatos, George Charitopoulos, Xinyu Niu, Wayne Luk Marco D .Santambrogio, Donatella Sciuto, Muhammed Al Kadi, Michael Huebner, Tobias Becker, Georgi Gaydadjiev, Andreas Brokalakis, Antonis Nikitakis, Alex J. W. Thom, Elias Vansteenkiste, Dirk Stroobandt

 

Abstract: To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low re- configuration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe’s competitive advantage and leadership in the field.

 

Presenter:    Catalin Ciobanu

 

Contact:       Catalin Ciobanu (c.b.ciobanu@uva.nl)

Project:        ANTAREX

 

Title:             ANTAREX - AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems

 

Authors:       Cristina Silvano, Giovanni Agosta, Andrea Bartolini, Andrea Beccari, Luca Benini, João M. P. Cardoso, Carlo Cavazzoni, Jan Martinovic, Gianluca Palermo, Martin Palkovic, Erven Rohou, Nico Sanna, and Katerina Slaninova


 

Abstract:      The main goal of the ANTAREX project is to express by a Domain Specific Language (DSL) the application self-adaptivity and to runtime manage and autotune applications for green and heterogeneous High Performance Computing (HPC) systems up to the Exascale level. Key innovations of the project include the introduction of a separation of concerns between self-adaptivity strategies and application functionalities. The DSL approach will allow the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management.

 

Presenter:    Cristina Silvano

 

Contact:       Cristina Silvano (silvano@elet.polimi.it)

Project:        READEX

 

Title:             READEX - Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing

 

Authors:       Yury Oleynik, Michael Gerndt, Joseph Schuchar, Per Gunnar Kjeldsberg, and Wolfgang E. Nagel

 

Abstract:      Efficiently utilizing the resources provided on cur- rent and future Exascale systems will be a challenging task, potentially causing a large amount of underutilized resources and wasted energy. A promising potential to improve efficiency of HPC applications stems from the significant degree of dynamic behaviour, e.g., run-time alternation in application resource requirements in HPC workloads. Manually detecting and leveraging this dynamism to improve performance and energy-efficiency is a tedious task that is commonly neglected by developers. However, using an automatic optimization approach, application dynamism can be analyzed at design-time and used to optimize system configurations at run-time.

 

Presenter:    Yury Oleynik

 

Contact:       Yury Oleynik (oleynik@in.tum.de)

Project:        MANGO

 

Title:             The MANGO FET-HPC Project: An Overview

 

Auhtors:       Jose ́ Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso,
Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, and Davide Zoni


 

Abstract:      In this paper, we provide an overview of the MANGO project and its goal. The MANGO project aims at addressing power, performance and predictability (the PPP space) in future High-Performance Com- puting systems. It starts from the fundamental intuition that effective techniques for all three goals ultimately rely on customization to adapt the computing resources to reach the desired Quality of Service (QoS). From this starting point, MANGO will explore different but interrelated mechanisms at various architectural levels, as well as at the level of the system software. In particular, to explore a new positioning across the PPP space, MANGO will investigate system-wide, holistic, proactive thermal and power management aimed at extreme-scale energy efficiency.

Presenter:    Giovanni Agosta

                    

Contact:       Giovanni Agosta (agosta@elet.polimi.it)

 

Special Sessions on EU-Funded Projects on Embedded Systems: Platforms, Health-care and Assisted Livings

Project:        RADIO

 

Title:             A Holistic Approach for Advancing Robots in Ambient Assisted Living Environments

 

Authors:       Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Göhringer, Michael Hübner, Georgios Keramidas, Christos Antonopoulos, Nikolaos S. Voros

 

Abstract:      Due to the demographic change in western society, new challenges regarding healthcare of the elderly population are at the verge of surfacing. Since young people are not capable of sustaining an adequate healthcare for elderly people, new healthcare fields have to be devised. Thanks to recent advances in information and communication technology, a low-cost infrastructure for supporting the elderly in their domestic environment will become possible. The EU project RADIO tackles the design of an old age compliant smart home environment and the integration of a mobile robot platform as assistant to an elderly person. Apart from this, the robot also functions as a mobile sensor platform. Under this context, unobtrusiveness is of paramount importance since the robot should be a natural participant of patients’ daily life. This paper discusses such a healthcare facility, analyses its requirements and poses the challenges towards this direction.

 

Presenter:    Fynn Schwiegelshohn (Fynn.Schwiegelshohn@ruhr-uni-bochum.de)

 

Bio:               Fynn Schwiegelshohn is  an assistant researcher at the chair of Embedded Systems of Information Technology (ESIT) in Bochum since May 2013. Before joining Prof. Dr.-Ing Michael Hübner’s team, he studied Electrical Engineering and Information Technology at the Technical University Dortmund where he received his Bachelor degree in 2010 and his Master degree in 2012. His current research interests lie in the exploration of applications which benefit from dynamic and partial reconfiguration.

                    

Contact:       Diana Goeringher (diana.goehringer@rub.de)

Project:        AEGLE

 

Title:             AEGLE: Advancing Integrated and Personalized Healthcare Services, The AEGLE Approach

 

Authors:       Andreas Raptopoulos, Vasileios Tsoutsouras, and Dimitrios Soudris

 

Abstract:      The AEGLE project aims to advance integrated and personalized healthcare services, by innovatively handling big-biodata both at the cloud and at local healthcare sites. At the local level, AEGLE will focus on real-time processing of large volumes of raw data originating from patient monitoring services. Then at the cloud level, AEGLE will offer an experimental big data research platform to data scientists, workers and data professionals across Europe. This paper presents the AEGLE’s approach to healthcare, along with the medical test cases and underlying technologies used in the project.

 

Presenter:    Vasileios Tsoutsouras

 

Bio:               Mr. Vasileios Tsoutsouras received his diploma in Electrical and Computer Engineering from the National Technical University of Athens in 2013. His Diploma Thesis focused on the management of resources in many-core NoC platforms. Its outcome was presented as a paper in DAC 2013 and received a HiPEAC award. Since 2014 he is a PhD student in Microprocessors and Digital Systems Laboratory of the Institute of Communication and Computer Systems (ICCS) of National Technical University of Athens. His main research include many-core architectures, run-time resource management, dynamic memory management and embedded systems design. He is principal investigator in two European funded projects regarding wearable medical devices and acceleration of medical data analytics.

 

Contact:       Dimitrios Soudris (dsoudris@microlab.ntua.gr)

Project:        AXIOM

 

Title:             Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

 

Authors:       Roberto Giorgi

 

Abstract:     Normally, Embedded System toolchains are highly customized for a specific System-on-Chip (SoC). Due to the higher energy efficiency of on-chip operations, the typical way to pass from one embedded-system generation to the other, is changing the SoC and eventually use another toolchain. We are exploring the feasibility and trade-offs in designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing its scalability through clusters of SBCs and while keeping the same programming model of the SBC. This board is based on FPGAs and embedded processors and its key points are: i) a fast custom interconnect for board-to-board communication  and ii) an easy programmable environment which could allow us both to off-load code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, to distribute the computation across boards. A key problem to deploy successfully this paradigm is to properly distribute the threads across several boards without explicit intervention of the programmer. In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can eventually double the performance by simply connecting two boards and without the need of: i) changing the basic hardware components (e.g., a different System-On-Chip), ii) changing the programming model to follow the vendor specific toolchain. Our approach is to try reducing the data movement across boards. The first experiments confirm the feasibility of our approach.

 

Presenter:    Roberto Giorgi

 

Bio:               Roberto Giorgi is an Associate Professor at Department of Information Engineering, University of Siena, Italy. He was Research Associate at the University of Alabama in Huntsville, USA. He received his PhD in Computer Engineering and his Master in Electronics Engineering, Magna cum Laude both from University of Pisa, Italy. He is the coordinator of the European Project AXIOM. He coordinated the TERAFLUX project in the area of Future and Emerging Technologies for Teradevice Computing. He is participating in the European projects HiPEAC (High Performance Embedded-system Architecture and Compiler) and SARC (Scalable ARChitectures), ERA (Embedded Reconfigurable Architectures). He took part in ChARM project, developing software for performance evaluation of ARM-processor based embedded systems with cache memory. He has been selected by the European Commission as an independent expert. His current interests include Computer Architecture themes such as Embedded Systems, Multiprocessors, Memory System Performance, Workload Characterization. He is a Lifetime member of ACM and a Senior Member of the IEEE, IEEE Computer Society.

 

Contact:       Roberto Giorgi (giorgi@dii.unisi.it)