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Keynote
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Special
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Program
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Wednesday, October 10 |
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08:15 - 08:40 |
Registration |
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08:40 - 09:00 |
Welcome Session |
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09:00 - 10:00 |
Keynote Speaker 1 Tools for Embedded Systems programming: from Research to Development Orlando Moreira, GrAI Matter Labs, The Netherlands Chair: Emmanuel Casseau, University of Rennes 1, France |
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10:00 - 10:45 |
Coffee Break |
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10:45 - 12:30 |
Session W1: Architectures for efficient numerical computation Session Chair: Lionel
Lacassagne, University Pierre et Marie Curie, France Design and Open Source Implementation of a Reconfigurable Hardware Model Predictive Controller using Online Optimization Florian Kästner and Michael Hübner Efficient Architecture for Implementation of Hermite Interpolation on FPGA Gibin Chacko George, Sriyash Caculo, Abhishek Moitra and Amalin Prince Efficient Solving of Markov Decision Processes on GPUs using Parallelized Sparse Matrices Adrian Sapio, Shuvra Bhattacharyya and Marilyn Wolf POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA Ahmed Abdelsalam, Ahmed Elsheikh, Jean-Pierre David and J.M. Pierre Langlois |
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12:30 - 14:00 |
Lunch |
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14:00 - 15:20 |
Session W2: Implementation of video processing algorithms 1 Session Chair: Bertrand
Le Gal, Université de Bordeaux, France Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures Andrea Petreto, Arthur Hennequin, Thomas Koehler, Thomas Romera, Yohan Fargeix, Boris Gaillard, Manuel Bouyer, Quentin Meunier and Lionel Lacassagne FPGA-based Real Time Embedded Hough Transform Architecture for circles detection Orlando Luis Chuquimia Camacho, Andrea Pinna, Xavier Dray and Bertrand Granado Real-time implementation of context image processing operations for 4K video stream in Zynq UltraScale+ MPSoC Marcin Kowalczyk, Dominika Przewłocka and Tomasz Kryjak |
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15:20 - 15:50 |
Coffee Break |
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15:50 - 17:10 |
Session W3: Implementation of video processing algorithms 2 Session Chair: Tomasz
Kryjak, AGH University of Science and Technology, Poland A Low Power Versatile Video Coding Fractional Interpolation Hardware Ahmet Can Mert, Ercan Kalali and Ilker Hamzaoglu Comparison of Lane Detection Algorithms for ADAS using Embedded Hardware Architectures Marc Reichenbach, Lukas Liebischer, Steffen Vaas and Dietmar Fey Implementation of a real-time image-based vibration detection and adaptive filtering on an FPGA Kazuya Uetsuhara, Akane Tahara, Taito Manabe and Yuichiro Shibata |
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17:10 - 18:30 |
Break |
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18:30 - 20:30 |
Demo Night, FEUP Room I-105 Chair: José Carlos Alves, University of Porto / INESC TEC,
Portugal Low latency wireless closed loop control of an inverted pendulum Sebastian Uziel, Philipp Schulz, Michael Katzschmann, Thomas Elste and Benjamin Eichhorn Speed-up different applications using half floats on Nvidia GPUs Mickaël Seznec and Nicolas Gac Hardware Acceleration of Face Detection Using a Deep Convolutional Neural Network - a demo Dominika Przewlocka and Tomasz Kryjak Real-time implementation of contextual image processing operations for 4K video stream in Zynq UltraScale+ MPSoC - a demo Marcin Kowalczyk, Dominika Przewlocka and Tomasz Kryjak Embedded vision system for automated drone landing site detection - a demo Patryk Fraczek, Andre Mora and Tomasz Kryjak Hardware - software implementation of a SFM module for navigation an unmanned aerial vehicles - a demo Karol Radwan, Tomasz Kryjak and Marek Gorgon Hardware implementation of multi-scale Lucas-Kanade optical flow computation algorithm - a demo Krzysztof Blachut, Tomasz Kryjak and Marek Gorgon Real-time evaluation of NB-LDPC codes thanks to HLS-based hardware emulation Hassan Harb, Emmanuel Boutillon and Bertrand Le Gal Real-time analysis of living biological cell activity Safouane Noubir, Yannick Bornat and Bertrand Le Gal Rapid Prototyping of Approximate Signal Processing Using Stochastic Processors on FPGAs Rui Policarpo Duarte, Mário Véstias and Horacio Neto |
Thursday, October 11 |
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08:30 - 08:40 |
Registration |
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08:40 - 09:00 |
Announcements |
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09:00 - 10:00 |
Making the transition from sensors
to sensor systems software Simon Dobson, University of St Andrews,
UK Chair: Pierre Langlois, Polytechnique
Montréal, Canada |
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10:00 - 10:45 |
Coffee Break |
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10:45 - 12:30 |
Session T1: European research projects Session Chair: João Canas Ferreira, Univ. do Porto and INESC TEC, Portugal Low Power Image Processing Applications on FPGAs using Dynamic Voltage Scaling and Partial Reconfiguration Ariel Podlubne,
Julian Haase, Lester Kalms, Goekhan
Akguen, Muhammad Ali, Habib Ul
Hasan Khan, Ahmed Kamal and Diana Goehringer The VINEYARD integrated framework for heterogeneous cloud applications: The BrainFrame case Harry Sidiropoulos, George Chatzikonstantis, Dimitrios Soudris and Christos Strydis Exploiting eXascale Technology with Reconfigurable Architectures Florian Fricke, Jose Gabriel de F. Coutinho, Michael Huebner AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications Hamid Arabnejad, João Bispo, Jorge G. Barbosa, João M. P. Cardoso |
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12:30 - 14:00 |
Lunch |
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14:00 - 15:20 |
Session T2: GPU
acceleration of algorithms Session Chair: Bertrand
Granado, Université
Pierre et Marie Curie, France A new connected components labelling and analysis algorithm for GPUs Arthur Hennequin, Lionel Lacassagne, Laurent Cabaret and Quentin Meunier Exploring performance improvement opportunities in directive-based GPU programming Rokiatou Diarra, Alain Merigot and Bastien Vincke GPU based Quarter Spectral Correlation Density Function Scott Marshall, Garrett Vanhoy, Ali Akoglu, Tamal Bose and Bo Ryu |
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15:20 - 15:50 |
Coffee Break and Poster Session European research projects |
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15:50 - 16:15 |
DASIP2019 Presentation |
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16:30 – 17:00 |
Bus transportation from FEUP/INESC TEC to Port Wine Cellar “Caves Ferreira” |
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17:30 - 18:30 |
Social Event: Visit to Port Wine Cellar “Caves Ferreira” |
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18:30 - 19:00 |
Cable car from “Cais de Gaia” to “Jardim do Morro” |
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19:00 - 19:30 |
Walking trip from “Jardim do Morro” to “São Bento” train station (depending of the weather conditions and of the time spent in the cellars) |
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19:30 - 20:00 |
Bus transportation to “Casa da Música” (from “São Bento” or from “Jardim do Morro”) |
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20:00 - 22:30 |
Dinner at the “Casa da Música” restaurant (at Porto Music Hall) |
Friday, October 12 |
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08:30 - 08:40 |
Registration |
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08:40 - 09:00 |
Announcements |
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09:00 - 10:00 |
Modular Arithmetic and Signal Processing: Emerging Applications and Technologies Leonel Sousa, IST/INESC-ID, Portugal Chair: José Carlos
Alves, University of Porto / INESC TEC, Portugal |
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10:00 - 10:30 |
Coffee Break |
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10:30 - 12:15 |
Session F1: Going beyond Moore's law Session Chair: Pierre Langlois, Polytechnique
Montréal, Canada Design flow for portable dataflow
programming of heterogeneous Platforms Jani Boutellier
and Henri Lunnikivi Accelerating Inference Phase in Ternary Convolutional Neural Networks using Configurable Processors Sivakumar Chidambaram, Alexandre Riviello, J.M. Pierre Langlois and Jean-Pierre David Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems Petr Dobias, Emmanuel Casseau and Oliver Sinnen Efficient task-based code generation for SDF graph execution on multicore processors Georgios Georgakarakos and Johan Lilius |
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12:15 - 12:45 |
Closing Session and Best Paper and Best Demo Awards |
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12:45 - 14:30 |
Lunch |
Poster Presentations |
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Poster Session: European research projects Thursday, October 11: 15:20 - 15:50 Session Chairs: João Canas Ferreira, University of Porto / INESC TEC, Portugal Low Power Image Processing
Applications on FPGAs using Dynamic Voltage Scaling and Partial
Reconfiguration Ariel Podlubne,
Julian Haase, Lester Kalms, Goekhan
Akguen, Muhammad Ali, Habib Ul
Hasan Khan, Ahmed Kamal and Diana Goehringer The VINEYARD integrated framework for
heterogeneous cloud applications: The BrainFrame
case Harry Sidiropoulos, George Chatzikonstantis, Dimitrios Soudris and Christos Strydis Exploiting eXascale Technology with Reconfigurable Architectures Florian Fricke, Jose Gabriel de F. Coutinho, Michael Huebner AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications Hamid Arabnejad, João Bispo, Jorge G.
Barbosa, João M. P. Cardoso |